
`define AXI_ADDR_WIDTH      32
`define AXI_DATA_WIDTH      64
`define AXI_ID_WIDTH        4
`define AXI_USER_WIDTH      1
`timescale 1ns/100ps

module Vostok564_tb();

reg                 clock,reset;      
wire aw_ready;
wire aw_valid;
wire [`AXI_ADDR_WIDTH-1:0] aw_addr;
wire [2:0] aw_prot;
wire [`AXI_ID_WIDTH-1:0] aw_id;
wire [`AXI_USER_WIDTH-1:0] aw_user;
wire [7:0] aw_len;
wire [2:0] aw_size;
wire [1:0] aw_burst;
wire aw_lock;
wire [3:0] aw_cache;
wire [3:0] aw_qos;
wire [3:0] aw_region;

wire w_ready;
wire w_valid;
wire [`AXI_DATA_WIDTH-1:0] w_data;
wire [`AXI_DATA_WIDTH/8-1:0] w_strb;
wire w_last;
wire [`AXI_USER_WIDTH-1:0] w_user;

wire b_ready;
wire b_valid;
wire [1:0] b_resp;
wire [`AXI_ID_WIDTH-1:0] b_id;
wire [`AXI_USER_WIDTH-1:0] b_user;

wire ar_ready;
wire ar_valid;
wire [`AXI_ADDR_WIDTH-1:0] ar_addr;
wire [2:0] ar_prot;
wire [`AXI_ID_WIDTH-1:0] ar_id;
wire [`AXI_USER_WIDTH-1:0] ar_user;
wire [7:0] ar_len;
wire [2:0] ar_size;
wire [1:0] ar_burst;
wire ar_lock;
wire [3:0] ar_cache;
wire [3:0] ar_qos;
wire [3:0] ar_region;

wire r_ready;
wire r_valid;
wire [1:0] r_resp;
wire [`AXI_DATA_WIDTH-1:0] r_data;
wire r_last;
wire [`AXI_ID_WIDTH-1:0] r_id;
wire [`AXI_USER_WIDTH-1:0] r_user;

reg   [63:0]	        sram_rdata;
/********** 输出信号 **********/
wire 					sram_ren;
wire  [3:0]			sram_arsize;
wire  [31:0]			sram_araddr;

wire 					sram_wen;
wire  [3:0]			sram_awsize;
wire  [31:0]			sram_awaddr;
wire  [63:0]			sram_wdata;

reg [31:0]memcore[512*1024-1:0];
reg [31:0]cyclecnt;
integer i;
initial 
begin
    $dumpfile("./temp/Vostok564_tb.vcd");
    $dumpvars();
    for(i=0;i<512*1024;i=i+1)
    begin
        memcore[i]=$random;
    end
    $readmemh("D:/Projects/vostok564/TestBin/microbench.bin.hex",memcore,19'h0,19'd65535);
    #0 clock=0;reset=1;cyclecnt=0;
    #105 reset=0;
end
always #10 clock=~clock;

always @(posedge clock)
begin
    if(sram_ren)
        sram_rdata<={memcore[{sram_araddr[21:3],1'b1}],memcore[{sram_araddr[21:3],1'b0}]};
    else
        sram_rdata<=sram_rdata;
    

end
Vostok564_top DUT(
//----------------------Global signal---------------------
    .Core_CLK(clock),   //Core clock (PRV564 kernal's clock)
    .Core_RST(reset),   //Core reset(), async
//-----------------------AXI interface---------------------
    //output [`AXI_USER_WIDTH-1:0]        `AXI_TOP_INTERFACE(aw_user),
    .o_AXI_awid(aw_id),
    .o_AXI_awaddr(aw_addr),
    .o_AXI_awlen(aw_len),
    .o_AXI_awsize(aw_size),
    .o_AXI_awburst(aw_burst),
    .o_AXI_awvalid(aw_valid),
    .i_AXI_awready(aw_ready),
//---------------------写数据通道-----------------------------
    .o_AXI_wdata(w_data),
    .o_AXI_wstrb(w_strb),
    .o_AXI_wlast(w_last),
    .o_AXI_wvalid(w_valid),
    .i_AXI_wready(w_ready),
//----------------------写回复通道-------------------------------	
//input  [`AXI_USER_WIDTH-1:0]        `AXI_TOP_INTERFACE(b_user),
    .i_AXI_bid(b_id),
    .i_AXI_bresp(b_resp),
    .i_AXI_bvalid(b_valid),
    .o_AXI_bready(b_ready),
//---------------------读地址通道-----------------------------------	
    //output [`AXI_USER_WIDTH-1:0]        `AXI_TOP_INTERFACE(ar_user),
    .o_AXI_arid(ar_id),
    .o_AXI_araddr(ar_addr),
    .o_AXI_arlen(ar_len),
    .o_AXI_arsize(ar_size),
    .o_AXI_arburst(ar_burst),
    .o_AXI_arvalid(ar_valid),
    .i_AXI_arready(ar_ready),
//----------------------读数据通道----------------------------------
    //input  [`AXI_USER_WIDTH-1:0]        `AXI_TOP_INTERFACE(r_user)
    .i_AXI_rid(r_id),
    .i_AXI_rdata(r_data),
    .i_AXI_rresp(r_resp),
    .i_AXI_rlast(r_last),
    .i_AXI_rvalid(r_valid),
    .o_AXI_rready(r_ready)
);





axi_slave_if#(  .DATA_WIDTH(64),             //数据位宽
            .ADDR_WIDTH(32),               //地址位宽              
            .ID_WIDTH  (4),               //ID位宽
            .USER_WIDTH(1)             //USER位宽
)TEST_RAM_INTERPRETER(
//     /********* 时钟&复位 *********/
// 	input                       
.ACLK(clock),
// 	input      	                
.ARESETn(!reset),
// 	/******** AXI总线信号 ********/
//     //写地址通道
// //	input      [ID_WIDTH-1:0]  
.AWID(aw_id),
// 	input	   [ADDR_WIDTH-1:0] 
.AWADDR(aw_addr),
// 	input	   [7:0]            
.AWLEN(aw_len),
// 	input	   [2:0]            
.AWSIZE(aw_size),
// 	input	   [1:0]	        
.AWBURST(aw_burst),
// //	input	  	                AWLOCK(aw_lock),
// //	input	   [3:0]	        AWCACHE(aw_cache),
// //	input	   [2:0]	        AWPROT(aw_prot),
// //	input	   [3:0]	        AWQOS(aw_qos),
// //	input	   [3:0]            AWREGION(aw_region),
// //	input	   [USER_WIDTH-1:0]	AWUSER(aw_user),
// 	input	 	                
.AWVALID(aw_valid),
// 	output    	                
.AWREADY(aw_ready),
// 	//写数据通道                
// //	input	   [ID_WIDTH-1:0]   .WID(),
// 	input	   [DATA_WIDTH-1:0] 
.WDATA(w_data),
// 	input	   [STRB_WIDTH-1:0] 
.WSTRB(w_strb),
// 	input		                
.WLAST(w_last),
// //	input	   [USER_WIDTH-1:0]	WUSER(w_user),
// 	input	  	                
.WVALID(w_valid),
// 	output    	                
.WREADY(w_ready),
// 	//写响应通道                
// //	output     [ID_WIDTH-1:0]   
.BID(b_id),
// 	output     [1:0]            
.BRESP(b_resp),
// //	output     [USER_WIDTH-1:0]	BUSER(b_user),
// 	output    	                
.BVALID(b_valid),
// 	input	  	                
.BREADY(b_ready),
// 	//读地址地址                
// //	input	   [ID_WIDTH-1:0]   
.ARID(ar_id),
// 	input	   [ADDR_WIDTH-1:0] 
.ARADDR(ar_addr),
// 	input	   [7:0]            
.ARLEN(ar_len),
// 	input	   [2:0]	        
.ARSIZE(ar_size),
// 	input	   [1:0]	        
.ARBURST(ar_burst),
// //	input	  	                ARLOCK(ar_lock),
// //	input	   [3:0]	        ARCACHE(ar_cache),
// //	input	   [2:0]            ARPROT(ar_prot),
// //	input	   [3:0]	        ARQOS(ar_qos),
// //	input	   [3:0]	        ARREGION(ar_region),
// //	input	   [USER_WIDTH-1:0]	ARUSER(ar_user),
// 	input	  	                
.ARVALID(ar_valid),
// 	output    	                
.ARREADY(ar_ready),
// 	//读数据通道                
// //	output     [ID_WIDTH-1:0]	
.RID(r_id),
// 	output     [DATA_WIDTH-1:0]	
.RDATA(r_data),
// 	output     [1:0]	        
.RRESP(r_resp),
// 	output    	                
.RLAST(r_last),
// //	output     [USER_WIDTH-1:0] RUSER(r_user),
// 	output                      
.RVALID(r_valid),
// 	input	 	                
.RREADY(r_ready),
// 	/********** DFT信号 **********/
// 	input						bist_en(),
// 	input						dft_en(),
// 	output						bist_done(),
// 	output		[7:0]			bist_fail
// input   [63:0]	        
.sram_rdata(sram_rdata),
// /********** 输出信号 **********/
// output 					
.ren(sram_ren),
// output  [3:0]			
.arsize(sram_arsize),
// output  [31:0]			
.araddr(sram_araddr),

// output 					
.wen(sram_wen),
// output  [3:0]			
.awsize(sram_awsize),
// output  [31:0]			
.awaddr(sram_awaddr),
// output  [63:0]			
.wdata(sram_wdata)
);  
endmodule